As integrated circuits, and systems employing groups of such circuits, become more complex it becomes desirable, if not imperative, to design testing facilities into them. One design process which has been developed to facilitate testing of an integrated circuit is the so-called "Scan Design", wherein each of the flip-flops (storage elements) in the integrated circuits has a multiplexer associated with it. This allows all of the flip-flops to be connected in series and "scanned", thus allowing one both to control and to observe all storage elements in the circuit. "Scan design" is most effective when the integrated circuit functions synchronously, i.e., all of the aforementioned flip-flops or storage elements are clocked by the same phase of one master clock. Unfortunately, with complex integrated circuits, it is difficult to achieve the reliable transfer of data between synchronously clocked storage elements when the time taken for the clock signal to reach one storage element from the clock source might be different from the time taken to reach another storage element. Because clock signals typically must be routed to all parts of the integrated circuit, and generally have high fan-out loading, they must often be re-buffered, perhaps several times, by a series of progressively larger buffers. Each buffer delays the signal by an amount which depends upon its load. Moreover, since different branches or paths will have different line resistances, a significant skew can result between the clock signals arriving at the remote storage elements. The delays introduced by re-buffering may lead to a so-called "race condition", wherein the data signal and the clock signal change at the same time.
Various approaches have been employed to ameliorate this problem of distributing clock signals in complex systems and integrated circuits. For example, Eby G. Friedman and Scott Powell discussed the problems of clock generation and distribution in such an environment in a paper entitled "Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI, IEEE Journal of Solid-State Circuits", Vol. S.C.-21, No. 2, April, 1986, which is incorporated herein by reference.
Robust two-edge timing can be achieved by inverting the clock signal to every second flip-flop in a data path, but this introduces considerable complication in the design of a circuit if it is to be testable by means of scan design.
Clocking schemes based on two-phase flip-flops can often provide robust timing but suffer from the disadvantage of requiring the generation of two clock phases and guaranteeing that their active levels are non-overlapping. One conventional method of generating a two-phase clock is to start with a double speed clock and divide it down to generate the non-overlapping pulses of the two clock signals. Disadvantages of this arrangement are the need for the higher speed clock and an additional control input to define the relative phase positions of the two phase clock signals. The amount of non-overlap is fixed at one-quarter of the clock period.
Another way of generating the two-phase clock signal is based upon the SR latch which involves a pair of NAND-gates one being clocked directly by the master clock and the other being clocked by the inverted master clock. The output of one NAND-gate is applied to the second input of the other, and vice versa. The outputs of the NAND-gates are also the respective two-phase clock signals. Although such an arrangement produces two phase clock signals which are non-overlapping, a disadvantage is that it is a minimum non-overlap at all edges. Such minimum non-overlap restricts the arrangement to localized areas of a design and also limits performance because the active following edge of the second clock signal is dependent upon the first clock signal and not directly upon the master clock. Moreover, the arrangement is not suited for communication between major blocks within an integrated circuit.
An object of the present invention is to mitigate these disadvantages.